`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Wuhan Unversity
// Engineer: Yu Zihao
// 
// Create Date: 2021/08/01 16:51:00
// Design Name: 
// Module Name: shifter
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description:
//    shift | Operation
//    00    | B
//    01    | B shifted left 1-bit, least significant bit is zero
//    10    | B shifted right 1-bit, most significant bit, MSB, is 0
//    11    | B shifted right 1-bit, MSB is copy of B[15]
// Dependencies: 
// 
// Revision: V1.0
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module shifter(in,shift,sout);
    input [15:0] in;
    input [1:0] shift;
    output [15:0] sout;
    
    reg [15:0] newloadb;
    assign sout = newloadb;
    
    always @(*) begin
        case(shift)
            2'b00 : {newloadb}={in};
            2'b01 : {newloadb[15:1],newloadb[0]}={in[14:0],1'b0};
            2'b10 : {newloadb[14:0],newloadb[15]}={in[15:1],1'b0};
            2'b11 : {newloadb[14:0],newloadb[15]}={in[15:1],in[15]};
        endcase
    end

endmodule
